Basic SDRAM controller for Terasic DE2 board
I think I pulled this one off quite nicely. The following is a controller for the 8 Megabyte SDRAM that the DE2 board uses.
- Basic command queue ("run this when possible")
- Read / write support
- Automatic refresh
- Uses burst of only one word, it is in other words quite slow
- Hardcoded to work with 50 MHz and CAS 2
The controller is very very simple and always executes the read and write operations as pre-charge variants which will close the activated row after the operation. The result of this is that a single read of 2 bytes will take 5 clock cycles (activate, read, CAS 2, actual read) - a write will take 3 (activate, write, recovery).
I'm inclined to create something more intelligent, faster and using the other features that this SDRAM module has to offer - but this will do for now.